1. Field of the Invention
The present invention relates to a semiconductor storage device. More particularly, the present invention relates to a semiconductor storage device equipped with an ECC function.
2. Description of the Related Art
There is known an ECC (error correction code) circuit mounted on a semiconductor storage device such as a DRAM. The ECC circuit can not only detect a memory error merely but also specify a position (bit) of an error in data and correct it to a correct value. Specifically, the ECC circuit calculates information referred to as “error correction code (ECC)” to the data in writing the data. The calculated ECC is stored in a memory space. When the data is then read, the ECC circuit detects and corrects the error of the read data by referring to the ECC previously calculated.
The data width of write data required for calculating the ECC is previously determined. For example, when a data bus width is 64 bits, one ECC is calculated for the write data of 64 bits. The number of bits of the calculated ECC is determined by a predetermined algorithm. In this case, the number of bits is 8 bits. Therefore, when the data of 256 bits is written, the total number of the bits of the calculated four ECCs is 32 bits.
According to the algorithm, the number of bits of the calculated ECC tends to be slowly increased with the increase of the width of the write data. Japanese Laid-Open Patent Application JP-A-Heisei, 11-102326 discloses a technique for suppressing the increase of the ECC using this tendency. According to this technique, one ECC is calculated in a data unit to which burst-write is carried out. For example, when the data bus width is 64 bits and the burst length is 4, one ECC is calculated for data of 256 bits. In this case, the number of bits of the calculated ECC is 9 bits, and the memory space occupied by the ECC is reduced as a whole.
We have now discovered the following facts. The present inventor has focused attention on a following point. In the ECC circuit, the data width for calculating the ECC is previously determined, and the predetermined data width is, for example, 64 bits. However, for example, only the data of 1 byte may be written for convenience of a system (Byte Write). Hereinafter, the writing of the data of under such a predetermined data width is referred to as “part writing”. Although the technique disclosed in the above-mentioned JP-A-Heisei, 11-102326 can reduce the ECC by putting the data together in calculating the ECC, the technique cannot deal with the part writing.